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| 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER The A6259KA and A6259KLW combine a 3-to-8 line CMOS decoder and accompanying data latches, control circuitry, and DMOS outputs in a multi-functional power driver capable of storing single-line data in the addressable latches or use as a decoder or demuliplexer. Driver applications include relays, solenoids, and other mediumcurrent or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are selectable with the CLEAR and ENABLE inputs. The addressed DMOS output inverts the DATA input with all unaddressed outputs remaining in their previous states. All of the output drivers are disabled (the DMOS sink drivers turned off) with the CLEAR input low and the ENABLE input high. The A6259KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Similar devices with reduced rDS(on) will be available as the A6A259. The A6259KA is furnished in a 20-pin dual in-line plastic package. The A6259KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applications. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85C. Data Sheet 26186.120 PRODUCT PREVIEW (Subject to change without notice) January 5, 1999 POWER GROUND LOGIC SUPPLY S 0 (LSB) OUT 0 OUT 1 OUT 2 OUT 3 S1 LOGIC GROUND POWER GROUND 1 2 3 4 LATCHES 20 VDD 19 18 17 LATCHES POWER GROUND CLEAR DATA OUT 7 OUT 6 OUT 5 OUT 4 ENABLE S 2 (MSB) POWER GROUND DECODER LOGIC 5 6 7 8 9 10 16 15 14 EN 13 12 11 Dwg. PP-050-2 Note that the A6259KA (DIP) and the A6259KLW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at T A = 25C Output Voltage, VO ............................... 45 V Output Drain Current, Continuous, IO .......................... 250 mA* Peak, IOM ................................. 750 mA* Peak, IOM ....................................... 2.0 A Single-Pulse Avalanche Energy, EAS ................................................. 75 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40C to +125C Storage Temperature Range, TS ................................. -55C to +150C *Each output, all outputs on. Pulse duration 100 s, duty cycle 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. FEATURES s 45 V Minimum Output Clamp Voltage s 250 mA Output Current (all outputs simultaneously) s 1.3 Typical rDS(on) s Low Power Consumption s Replacements for TPIC6259N and TPIC6259DW This document contains information on a product under development. Allegro MicroSystems, Inc. reserves the right to change or discontinue this product without notice. Always order by complete part number: Part Number Package A6259KA 20-pin DIP A6259KLW 20-lead SOIC RJA 55C/W 70C/W RJC 25C/W 17C/W 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER LOGIC SYMBOL ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 2.5 3 8 0 8M 0/7 2 G8 Z9 Z10 9,0D 10,0R 9,1D 10,1R 9,2D 10,2R 9,3D 10,3R 9,4D 10,4R 9,5D 10,5R 9,6D 10,6R 4 5 6 7 14 15 16 17 2.0 SU FF IX 1.5 SU FF IX 'A ', R 12 13 18 19 A= J 'LW ', R 55 C /W 1.0 J A= 70 C /W 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150 9,7D 10,7R Dwg. GS-004A Dwg. FP-046 VDD OUT IN Dwg. EP-010-15 Dwg. EP-063 LOGIC INPUTS DMOS POWER DRIVER OUTPUT FUNCTION TABLE Inputs CLEAR ENABLE DATA H H H L L L L L H L L H H L X H L X LATCH SELECTION TABLE Function Addressable Latch Memory 8-Line Demultiplexer Clear R = Previous State Addressed OUTPUT L H R L H H Other OUTPUTs R R R H H H Select Inputs Addressed S2 (MSB) S 1 S0 (LSB) OUTPUT L L L L H H H L L H H L L H L H L H L H L 0 1 2 3 4 5 6 L = Low Logic Level H = High Logic Level X = Irrelevant H H H 7 115 Northeast Cutoff, Box 15036 W Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1999, Allegro MicroSystems, Inc. 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER FUNCTIONAL BLOCK DIAGRAM D C1 CLR D C1 CLR S1 D C1 CLR D C1 CLR S2 (MSB) D C1 CLR D V DD C1 CLR LOGIC GROUND D C1 CLR DATA ENABLE (ACTIVE LOW) S0 (LSB) OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 LOGIC SUPPLY OUT 5 OUT 6 D C1 CLR OUT 7 POWER GROUND Dwg. FP-047-1 CLEAR (ACTIVE LOW) Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point. 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V, tir = tif 10 ns (unless otherwise specified). Limits Characteristic Logic Supply Voltage Output Breakdown Voltage Off-State Output Current Static Drain-Source On-State Resistance Symbol VDD V (BR)DSX IDSX Test Conditions Operating IO = 1 mA VO = 40 V VO = 40 V, T A = 125C Min. 4.5 45 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 5.0 -- 0.05 0.15 1.3 2.0 1.3 250 -- -- 625 140 650 400 15 150 Max. 5.5 -- 1.0 5.0 2.0 3.2 2.0 -- 1.0 -1.0 -- -- -- -- 100 300 Units V V A A mA A A ns ns ns ns A A rDS(on) IO = 250 mA, VDD = 4.5 V IO = 250 mA, VDD = 4.5 V, TA = 125C IO = 500 mA, VDD = 4.5 V (see note) Nominal Output Current Logic Input Current ION IIH IIL VDS(on) = 0.5 V, TA = 85C VI = VDD = 5.5 V VI = 0, VDD = 5.5 V IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF IO = 250 mA, CL = 30 pF VDD = 5.5 V, Outputs off VDD = 5.5 V, Outputs on Prop. Delay Time tPLH tPHL Output Rise Time Output Fall Time Supply Current tr tf IDD(OFF) IDD(ON) Typical Data is at VDD = 5 V and is for design information only. NOTE -- Pulse test, duration 100 s, duty cycle 2%. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS ENABLE Four modes of operation are selectable by controlling the CLEAR and ENABLE inputs as shown above. 50% DATA t PLH ADDRESSED OUTPUT t PHL 90% 10% In the addressable-latch mode, data at the DATA input is written into the addressed transparent latch. The addressed output inverts the data input with all other outputs remaining in their previous states. Dwg. WP-036 tr tf OUTPUT SWITCHING TIME In the memory mode, all outputs remain in their previous states and are unaffected by the DATA or address (Sn) inputs. To prevent entering erroneus data in the latches, ENABLE should be held HIGH while the address lines are changing. In the demultiplexing/decoding mode, the addressed output inverts the data input and all other outputs are OFF. In the clear mode, all outputs are OFF and are unaffected by the DATA or address (SN) inputs. ENABLE t su(D) DATA 50% 50% t h(D) t w(D) Dwg. WP-037 DATA INPUT REQUIREMENTS Data Active Time Before Enable (Data Set-Up Time), tsu(D) .............................................. 20 ns Data Active Time After Enable (Data Hold Time), th(D) ................................................... 20 ns Data Pulse Width, tw(D) ....................................................... 40 ns Input Logic High, VIH ................................................ 0.85VCC Input Logic Low, VIL ................................................. 0.15VCC Given the appropriate inputs, when DATA is LOW for a given address, the output is OFF; when DATA is HIGH, the output is ON and can sink current. 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER TEST CIRCUITS INPUT +15 V 0.11 tav IAS = 1.0 A IO DUT OUT VO V(BR)DSX VO(ON) Dwg. EP-066-1 E AS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 100 mH 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER TERMINAL DESCRIPTIONS Terminal No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name POWER GROUND LOGIC SUPPLY S0 OUT 0 OUT 1 OUT 2 OUT 3 S1 LOGIC GROUND POWER GROUND POWER GROUND S2 ENABLE OUT4 OUT5 OUT6 OUT7 DATA CLEAR POWER GROUND Function Reference terminal for output voltage measurements (OUT0-3). (VDD ) The logic supply voltage (typically 5 V). Binary-coded output-select input, least-significant bit. Current-sinking, open-drain DMOS output, address 000. Current-sinking, open-drain DMOS output, address 001. Current-sinking, open-drain DMOS output, address 010. Current-sinking, open-drain DMOS output, address 011. Binary-coded output-select input. Reference terminal for input voltage measurements. Reference terminal for output voltage measurements (OUT0-3). Reference terminal for output voltage measurements (OUT4-7). Binary-coded output-select input, most-significant bit. Mode control input; see Function Table. Current-sinking, open-drain DMOS output, address 100. Current-sinking, open-drain DMOS output, address 101. Current-sinking, open-drain DMOS output, address 110. Current-sinking, open-drain DMOS output, address 111. CMOS data input to the addressed output latch. When enabled, the addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW). Mode control input; see Function Table. Reference terminal for output voltage measurements (OUT4-7). NOTE -- Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point. 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER A6B259KA Dimensions in Inches (controlling dimensions) 20 11 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 BSC 10 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 20 11 0.355 0.204 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-20 mm NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER A6B259KLW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.5118 0.4961 0.050 BSC 0 TO 8 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 13.00 12.60 1.27 BSC 0 TO 8 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 6259 8-BIT ADDRESSABLE DMOS POWER DRIVER Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 |
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